1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although increase in memory storage capacity has been mainly achieved by reducing the dimension for each device (refinement), recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, in currently available ArF immersion lithography technology, for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement. However, the EUV exposure devices are expensive and infeasible in view of the costs. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, for example, Japanese Patent Laid-Open No. 2007-266143, U.S. Pat. No. 5,599,724, and U.S. Pat. No. 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (see, the patent documents listed above). Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple laminated conductive layers (word-line conductive layers) corresponding to gate electrodes, and pillar-like columnar semiconductors. Each of the columnar semiconductor layers serves as a channel (body) part of each of the transistors. Memory gate insulation layers that can store electric charges are provided around the columnar semiconductor layers. Such a configuration including laminated conductive layers, columnar semiconductors, and memory gate insulation layers is referred to as a “memory string”.
The semiconductor storage devices with such memory strings have laminated conductive layers formed in a stepwise manner in relation to each other, at respective ends in a predetermined direction parallel to the substrate. Furthermore, contact layers (contact plugs) extending from above the laminated conductive layers are formed on the top surfaces of the stepwise ends of the laminated conductive layers. The contact layers are provided to connect the laminated conductive layers with the conductive layers formed above the laminated conductive layers. This configuration is more advantageous in view of the costs because it does not require any lithography steps that would otherwise be critical in the manufacturing process. However, the contact layers have uneven depths because they are formed to reach the laminated conductive layers formed in a stepwise manner. It is thus desirable that an etching stopper material or the like is deposited on the stepwise ends of the laminated conductive layers to ensure that apertures with uneven depths are formed at a time. However, it is necessary to provide larger step widths of the stepwise ends, corresponding to the additional film thickness of the etching stopper material. That is, this has hampered further reduction in area occupied by the entire semiconductor storage devices (the entire chip area).